Electrical fuses are frequently included in integrated circuits. The fuses are blown in specific patterns to program certain integrated circuits. FIG. 1A illustrates one example of a conventional programmable fuse arrangement. As shown in FIG. 1A, the fuse 102 is disposed between a p-type transistor (PMOS) 104 and an n-type transistors (NMOS) 106. The first transistor 104 has its gate coupled to a bit line select line, its source coupled to a power supply, and its drain coupled to the fuse 102. The second transistor 106 has its source coupled to fuse 102, its gate coupled to a word line (WL), and its drain coupled to ground.
The fuse 102 is programmed by a logic zero being applied to the gate of PMOS transistor 104, which turns PMOS transistor 104 into a current-conducting ‘on’ state, and applying a programming pulse of a logic one to the gate of NMOS transistor 106, which transitions NMOS transistor 106 into a current-conducting ‘on’ state. The waveform for the programming signal, PGM, is illustrated in FIG. 1B. The logic zero at the gate of PMOS transistor 104 and the programming pulse at the gate of NMOS transistor 106 turns on transistors 104 and 106 such that current flows through fuse 102. The waveform for the fuse programming current is also shown in FIG. 1B. As shown in FIG. 1B, the programming current has a magnitude that is greater than the threshold of the fuse 102, which results in fuse 102 being blown or programmed. However, the conventional fuse arrangement illustrated in FIG. 1A frequently results in a varied resistance of the blown fuses especially across wide variations in processes, voltages, and temperatures (PVT). The large variations in resistance results in a narrower sensing margin making it more difficult to determine if a fuse has in fact been blown or programmed.
Accordingly, an improved fuse arrangement is desirable.